[RISC-V][PR target/123283] Wrap naked REG operands with a USE.

[RISC-V][PR target/123283] Wrap naked REG operands with a USE.

I was in the process of testing this patch when Andreas filed PR123283.

What's going on is we have patterns in sync.md which have naked operands:

(define_insn "subword_atomic_fetch_strong_<atomic_optab>"
  [(set (match_operand:SI 0 "register_operand" "=&r")   ;; old value at mem
    (match_operand:SI 1 "memory_operand" "+A"))        ;; mem location
   (set (match_dup 1)
    (unspec_volatile:SI
      [(any_atomic:SI (match_dup 1)
             (match_operand:SI 2 "arith_operand" "rI")) ;; value for op
       (match_operand:SI 3 "const_int_operand")]           ;; model
     UNSPEC_SYNC_OLD_OP_SUBWORD))
    (match_operand:SI 4 "arith_operand" "rI")          ;; mask
    (match_operand:SI 5 "arith_operand" "rI")          ;; not_mask
    (clobber (match_scratch:SI 6 "=&r"))               ;; tmp_1
    (clobber (match_scratch:SI 7 "=&r"))]              ;; tmp_2

Note carefully operands #4 and #5 and the fact they are a toplevel construct as
opposed to being an operand of another RTX.  That's a no-no.  They need to be
wrapped with a USE.

I spot-checked sync.md and found a few more instances.   Fixing the set I found
fixed the testsuite regressions I was seeing and also fixes the mis-compilation
of libgo.  Bootstrapped and regression tested on my BPI and Pioneer.  It's also
clean on the riscv64-elf and riscv32-elf targets in my tester.

	PR target/123283
gcc/
	* config/riscv/sync.md (subword_atomic_fetch_strong_nand): Add
	USEs for naked operands that might be pseudos.
	(subword_atomic_fetch_strong_<atomic_optab>): Likewise.
	(subword_atomic_exchange_strong): Likewise.
	(subword_atomic_cas_strong): Likewise.