[RISC-V][PR target/123278] Handle BF/HF modes in Andes 45 series pipeline description

So a standard run-of-the-mill case where we're testing modes to determine what
reservation to use in a pipeline model and modes were missing (BF/HF in this
case).

This adds the BF/HF cases to the fp_alu_s, fpu_mul_s and fpu_mac_s units for
the Andes 45 series.  It may ultimately be the case that even lower latencies
are available for these ops, but that's something folks with a better
understanding of the Andes 45 series uarch would need to tackle.

Tested on riscv32-elf and riscv64-elf. Given the nature of the change and the
fact that I expect to be out of the office most of the next few days, I'm going
to go ahead and push without waiting for pre-commit CI.  There's minimal risk.

	PR target/123278
gcc/
	* config/riscv/andes-45-series.md (andes_45_fpu_alu_s): Handle
	BF/HF modes too.
	(andes_45_fpu_mul_s, andes_45_fpu_mac_s): Likewise.

gcc/testsuite/
	* gcc.target/riscv/pr123278.c: New test.

diff --git a/gcc/config/riscv/andes-45-series.md b/gcc/config/riscv/andes-45-series.md
index 7693db84746bf09d29b01d1cdd34f0e5b1616038..cca9b3fba110bc21704591ddc55783ec00489af9 100644 (file)
--- a/gcc/config/riscv/andes-45-series.md
+++ b/gcc/config/riscv/andes-45-series.md
@@ -112,7 +112,7 @@
 (define_insn_reservation "andes_45_fpu_alu_s" 3
   (and (eq_attr "tune" "andes_45_series")
        (and (eq_attr "type" "fadd")
-           (eq_attr "mode" "SF")))
+           (eq_attr "mode" "BF,HF,SF")))
   "andes_45_fpu_arith")
 
 (define_insn_reservation "andes_45_fpu_alu_d" 4
@@ -124,7 +124,7 @@
 (define_insn_reservation "andes_45_fpu_mul_s" 3
   (and (eq_attr "tune" "andes_45_series")
        (and (eq_attr "type" "fmul")
-           (eq_attr "mode" "SF")))
+           (eq_attr "mode" "BF,HF,SF")))
   "andes_45_fpu_arith")
 
 (define_insn_reservation "andes_45_fpu_mul_d" 4
@@ -136,7 +136,7 @@
 (define_insn_reservation "andes_45_fpu_mac_s" 3
   (and (eq_attr "tune" "andes_45_series")
        (and (eq_attr "type" "fmadd")
-           (eq_attr "mode" "SF")))
+           (eq_attr "mode" "BF,HF,SF")))
   "(andes_45_pipe0 | andes_45_pipe1) + andes_45_fpu_fmac + andes_45_fpu_fmv + andes_45_fpu_fmis")
 
 (define_insn_reservation "andes_45_fpu_mac_d" 4

diff --git a/gcc/testsuite/gcc.target/riscv/pr123278.c b/gcc/testsuite/gcc.target/riscv/pr123278.c
new file mode 100644 (file)
index 0000000..78afa59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr123278.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-mcpu=xt-c910v2 -mtune=andes-n45 -O2" } */
+_Float16 f;
+
+void
+foo ()
+{
+  f *= 10;
+}