Sync DPDK's modifies.

1. igb_uio.
2. mlx5 drivers.
3. i40e drivers.
4. Freebsd-13.1.
5. sync dts/poetry.lock

diff --git a/dpdk/drivers/net/i40e/i40e_ethdev.c b/dpdk/drivers/net/i40e/i40e_ethdev.c
index 4ab9d6905daf4866f09661fecf280a15caabf0c3..2b40abcfbfcd7971a602f77fa29d63fcb9b5929a 100644 (file)
--- a/dpdk/drivers/net/i40e/i40e_ethdev.c
+++ b/dpdk/drivers/net/i40e/i40e_ethdev.c
@@ -1514,7 +1514,8 @@ eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
        }
        /* Firmware of SFP x722 does not support 802.1ad frames ability */
        if (hw->device_id == I40E_DEV_ID_SFP_X722 ||
-               hw->device_id == I40E_DEV_ID_SFP_I_X722)
+               hw->device_id == I40E_DEV_ID_SFP_I_X722 ||
+               hw->device_id == I40E_DEV_ID_10G_BASE_T_X722)
                hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
 
        PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",

diff --git a/dpdk/drivers/net/mlx5/linux/mlx5_ethdev_os.c b/dpdk/drivers/net/mlx5/linux/mlx5_ethdev_os.c
index 1d999ef66ba4145270ff595f000f4a270e76a2a3..ca886357657a8b90d472eb61a6bf54a3c42e277a 100644 (file)
--- a/dpdk/drivers/net/mlx5/linux/mlx5_ethdev_os.c
+++ b/dpdk/drivers/net/mlx5/linux/mlx5_ethdev_os.c
@@ -23,6 +23,7 @@
 #include <stdalign.h>
 #include <sys/un.h>
 #include <time.h>
+#include <dlfcn.h>
 
 #include <ethdev_driver.h>
 #include <bus_pci_driver.h>
@@ -1045,6 +1046,7 @@ mlx5_sysfs_check_switch_info(bool device_dir,
  * @return
  *   0 on success, a negative errno value otherwise and rte_errno is set.
  */
+static char *(*real_if_indextoname)(unsigned int, char *) = NULL;
 int
 mlx5_sysfs_switch_info(unsigned int ifindex, struct mlx5_switch_info *info)
 {
@@ -1065,7 +1067,16 @@ mlx5_sysfs_switch_info(unsigned int ifindex, struct mlx5_switch_info *info)
        char c;
        ssize_t line_size;
 
-       if (!if_indextoname(ifindex, ifname)) {
+       // for ff tools
+       if (!real_if_indextoname) {
+               real_if_indextoname = __extension__ (char *(*)(unsigned int, char *))dlsym(RTLD_NEXT, "if_indextoname");
+               if (!real_if_indextoname) {
+                       rte_errno = errno;
+                       return -rte_errno;
+               }
+       }
+
+       if (!real_if_indextoname(ifindex, ifname)) {
                rte_errno = errno;
                return -rte_errno;
        }

diff --git a/dpdk/drivers/net/mlx5/linux/mlx5_os.c b/dpdk/drivers/net/mlx5/linux/mlx5_os.c
index c6e5e7b42543bfd6509d0029df5b0a94b1040cb9..db5c95975cfd8425da5776cd74255c635d80ed1c 100644 (file)
--- a/dpdk/drivers/net/mlx5/linux/mlx5_os.c
+++ b/dpdk/drivers/net/mlx5/linux/mlx5_os.c
@@ -14,6 +14,7 @@
 #include <linux/sockios.h>
 #include <linux/ethtool.h>
 #include <fcntl.h>
+#include <dlfcn.h>
 
 #include <rte_malloc.h>
 #include <ethdev_driver.h>
@@ -2028,6 +2029,7 @@ close_nlsk_fd:
 
 #define SYSFS_MPESW_PARAM_MAX_LEN 16
 
+static char *(*real_if_indextoname)(unsigned int, char *) = NULL;
 static int
 mlx5_sysfs_esw_multiport_get(struct ibv_device *ibv, struct rte_pci_addr *pci_addr, int *enabled)
 {
@@ -2057,7 +2059,16 @@ mlx5_sysfs_esw_multiport_get(struct ibv_device *ibv, struct rte_pci_addr *pci_ad
                ifindex = mlx5_nl_ifindex(nl_rdma, ibv->name, i);
                if (!ifindex)
                        continue;
-               if (!if_indextoname(ifindex, ifname))
+
+               // for ff tools
+               if (!real_if_indextoname) {
+                       real_if_indextoname = __extension__ (char *(*)(unsigned int, char *))dlsym(RTLD_NEXT, "if_indextoname");
+                       if (!real_if_indextoname) {
+                               rte_errno = errno;
+                               return -rte_errno;
+                       }
+               }
+               if (!real_if_indextoname(ifindex, ifname))
                        continue;
                MKSTR(sysfs_if_path, "/sys/class/net/%s", ifname);
                if (mlx5_get_pci_addr(sysfs_if_path, &if_pci_addr))

diff --git a/dpdk/dts/poetry.lock b/dpdk/dts/poetry.lock
index f7b3b6d6027520326824027cf9589790b9dccae6..5f853601df5a67c779f2f78100b3c295eda358b3 100644 (file)
--- a/dpdk/dts/poetry.lock
+++ b/dpdk/dts/poetry.lock
@@ -1,4 +1,4 @@
-# This file is automatically @generated by Poetry 1.5.1 and should not be changed by hand.
+# This file is automatically @generated by Poetry 1.8.5 and should not be changed by hand.
 
 [[package]]
 name = "attrs"
@@ -189,47 +189,55 @@ files = [
 
 [[package]]
 name = "cryptography"
-version = "41.0.2"
+version = "44.0.1"
 description = "cryptography is a package which provides cryptographic recipes and primitives to Python developers."
 optional = false
-python-versions = ">=3.7"
-files = [
-    {file = "cryptography-41.0.2-cp37-abi3-macosx_10_12_universal2.whl", hash = "sha256:01f1d9e537f9a15b037d5d9ee442b8c22e3ae11ce65ea1f3316a41c78756b711"},
-    {file = "cryptography-41.0.2-cp37-abi3-macosx_10_12_x86_64.whl", hash = "sha256:079347de771f9282fbfe0e0236c716686950c19dee1b76240ab09ce1624d76d7"},
-    {file = "cryptography-41.0.2-cp37-abi3-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:439c3cc4c0d42fa999b83ded80a9a1fb54d53c58d6e59234cfe97f241e6c781d"},
-    {file = "cryptography-41.0.2-cp37-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:f14ad275364c8b4e525d018f6716537ae7b6d369c094805cae45300847e0894f"},
-    {file = "cryptography-41.0.2-cp37-abi3-manylinux_2_28_aarch64.whl", hash = "sha256:84609ade00a6ec59a89729e87a503c6e36af98ddcd566d5f3be52e29ba993182"},
-    {file = "cryptography-41.0.2-cp37-abi3-manylinux_2_28_x86_64.whl", hash = "sha256:49c3222bb8f8e800aead2e376cbef687bc9e3cb9b58b29a261210456a7783d83"},
-    {file = "cryptography-41.0.2-cp37-abi3-musllinux_1_1_aarch64.whl", hash = "sha256:d73f419a56d74fef257955f51b18d046f3506270a5fd2ac5febbfa259d6c0fa5"},
-    {file = "cryptography-41.0.2-cp37-abi3-musllinux_1_1_x86_64.whl", hash = "sha256:2a034bf7d9ca894720f2ec1d8b7b5832d7e363571828037f9e0c4f18c1b58a58"},
-    {file = "cryptography-41.0.2-cp37-abi3-win32.whl", hash = "sha256:d124682c7a23c9764e54ca9ab5b308b14b18eba02722b8659fb238546de83a76"},
-    {file = "cryptography-41.0.2-cp37-abi3-win_amd64.whl", hash = "sha256:9c3fe6534d59d071ee82081ca3d71eed3210f76ebd0361798c74abc2bcf347d4"},
-    {file = "cryptography-41.0.2-pp310-pypy310_pp73-macosx_10_12_x86_64.whl", hash = "sha256:a719399b99377b218dac6cf547b6ec54e6ef20207b6165126a280b0ce97e0d2a"},
-    {file = "cryptography-41.0.2-pp310-pypy310_pp73-manylinux_2_28_aarch64.whl", hash = "sha256:182be4171f9332b6741ee818ec27daff9fb00349f706629f5cbf417bd50e66fd"},
-    {file = "cryptography-41.0.2-pp310-pypy310_pp73-manylinux_2_28_x86_64.whl", hash = "sha256:7a9a3bced53b7f09da251685224d6a260c3cb291768f54954e28f03ef14e3766"},
-    {file = "cryptography-41.0.2-pp310-pypy310_pp73-win_amd64.whl", hash = "sha256:f0dc40e6f7aa37af01aba07277d3d64d5a03dc66d682097541ec4da03cc140ee"},
-    {file = "cryptography-41.0.2-pp38-pypy38_pp73-macosx_10_12_x86_64.whl", hash = "sha256:674b669d5daa64206c38e507808aae49904c988fa0a71c935e7006a3e1e83831"},
-    {file = "cryptography-41.0.2-pp38-pypy38_pp73-manylinux_2_28_aarch64.whl", hash = "sha256:7af244b012711a26196450d34f483357e42aeddb04128885d95a69bd8b14b69b"},
-    {file = "cryptography-41.0.2-pp38-pypy38_pp73-manylinux_2_28_x86_64.whl", hash = "sha256:9b6d717393dbae53d4e52684ef4f022444fc1cce3c48c38cb74fca29e1f08eaa"},
-    {file = "cryptography-41.0.2-pp38-pypy38_pp73-win_amd64.whl", hash = "sha256:192255f539d7a89f2102d07d7375b1e0a81f7478925b3bc2e0549ebf739dae0e"},
-    {file = "cryptography-41.0.2-pp39-pypy39_pp73-macosx_10_12_x86_64.whl", hash = "sha256:f772610fe364372de33d76edcd313636a25684edb94cee53fd790195f5989d14"},
-    {file = "cryptography-41.0.2-pp39-pypy39_pp73-manylinux_2_28_aarch64.whl", hash = "sha256:b332cba64d99a70c1e0836902720887fb4529ea49ea7f5462cf6640e095e11d2"},
-    {file = "cryptography-41.0.2-pp39-pypy39_pp73-manylinux_2_28_x86_64.whl", hash = "sha256:9a6673c1828db6270b76b22cc696f40cde9043eb90373da5c2f8f2158957f42f"},
-    {file = "cryptography-41.0.2-pp39-pypy39_pp73-win_amd64.whl", hash = "sha256:342f3767e25876751e14f8459ad85e77e660537ca0a066e10e75df9c9e9099f0"},
-    {file = "cryptography-41.0.2.tar.gz", hash = "sha256:7d230bf856164de164ecb615ccc14c7fc6de6906ddd5b491f3af90d3514c925c"},
+python-versions = "!=3.9.0,!=3.9.1,>=3.7"
+files = [
+    {file = "cryptography-44.0.1-cp37-abi3-macosx_10_9_universal2.whl", hash = "sha256:bf688f615c29bfe9dfc44312ca470989279f0e94bb9f631f85e3459af8efc009"},
+    {file = "cryptography-44.0.1-cp37-abi3-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:dd7c7e2d71d908dc0f8d2027e1604102140d84b155e658c20e8ad1304317691f"},
+    {file = "cryptography-44.0.1-cp37-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:887143b9ff6bad2b7570da75a7fe8bbf5f65276365ac259a5d2d5147a73775f2"},
+    {file = "cryptography-44.0.1-cp37-abi3-manylinux_2_28_aarch64.whl", hash = "sha256:322eb03ecc62784536bc173f1483e76747aafeb69c8728df48537eb431cd1911"},
+    {file = "cryptography-44.0.1-cp37-abi3-manylinux_2_28_armv7l.manylinux_2_31_armv7l.whl", hash = "sha256:21377472ca4ada2906bc313168c9dc7b1d7ca417b63c1c3011d0c74b7de9ae69"},
+    {file = "cryptography-44.0.1-cp37-abi3-manylinux_2_28_x86_64.whl", hash = "sha256:df978682c1504fc93b3209de21aeabf2375cb1571d4e61907b3e7a2540e83026"},
+    {file = "cryptography-44.0.1-cp37-abi3-manylinux_2_34_aarch64.whl", hash = "sha256:eb3889330f2a4a148abead555399ec9a32b13b7c8ba969b72d8e500eb7ef84cd"},
+    {file = "cryptography-44.0.1-cp37-abi3-manylinux_2_34_x86_64.whl", hash = "sha256:8e6a85a93d0642bd774460a86513c5d9d80b5c002ca9693e63f6e540f1815ed0"},
+    {file = "cryptography-44.0.1-cp37-abi3-musllinux_1_2_aarch64.whl", hash = "sha256:6f76fdd6fd048576a04c5210d53aa04ca34d2ed63336d4abd306d0cbe298fddf"},
+    {file = "cryptography-44.0.1-cp37-abi3-musllinux_1_2_x86_64.whl", hash = "sha256:6c8acf6f3d1f47acb2248ec3ea261171a671f3d9428e34ad0357148d492c7864"},
+    {file = "cryptography-44.0.1-cp37-abi3-win32.whl", hash = "sha256:24979e9f2040c953a94bf3c6782e67795a4c260734e5264dceea65c8f4bae64a"},
+    {file = "cryptography-44.0.1-cp37-abi3-win_amd64.whl", hash = "sha256:fd0ee90072861e276b0ff08bd627abec29e32a53b2be44e41dbcdf87cbee2b00"},
+    {file = "cryptography-44.0.1-cp39-abi3-macosx_10_9_universal2.whl", hash = "sha256:a2d8a7045e1ab9b9f803f0d9531ead85f90c5f2859e653b61497228b18452008"},
+    {file = "cryptography-44.0.1-cp39-abi3-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:b8272f257cf1cbd3f2e120f14c68bff2b6bdfcc157fafdee84a1b795efd72862"},
+    {file = "cryptography-44.0.1-cp39-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:1e8d181e90a777b63f3f0caa836844a1182f1f265687fac2115fcf245f5fbec3"},
+    {file = "cryptography-44.0.1-cp39-abi3-manylinux_2_28_aarch64.whl", hash = "sha256:436df4f203482f41aad60ed1813811ac4ab102765ecae7a2bbb1dbb66dcff5a7"},
+    {file = "cryptography-44.0.1-cp39-abi3-manylinux_2_28_armv7l.manylinux_2_31_armv7l.whl", hash = "sha256:4f422e8c6a28cf8b7f883eb790695d6d45b0c385a2583073f3cec434cc705e1a"},
+    {file = "cryptography-44.0.1-cp39-abi3-manylinux_2_28_x86_64.whl", hash = "sha256:72198e2b5925155497a5a3e8c216c7fb3e64c16ccee11f0e7da272fa93b35c4c"},
+    {file = "cryptography-44.0.1-cp39-abi3-manylinux_2_34_aarch64.whl", hash = "sha256:2a46a89ad3e6176223b632056f321bc7de36b9f9b93b2cc1cccf935a3849dc62"},
+    {file = "cryptography-44.0.1-cp39-abi3-manylinux_2_34_x86_64.whl", hash = "sha256:53f23339864b617a3dfc2b0ac8d5c432625c80014c25caac9082314e9de56f41"},
+    {file = "cryptography-44.0.1-cp39-abi3-musllinux_1_2_aarch64.whl", hash = "sha256:888fcc3fce0c888785a4876ca55f9f43787f4c5c1cc1e2e0da71ad481ff82c5b"},
+    {file = "cryptography-44.0.1-cp39-abi3-musllinux_1_2_x86_64.whl", hash = "sha256:00918d859aa4e57db8299607086f793fa7813ae2ff5a4637e318a25ef82730f7"},
+    {file = "cryptography-44.0.1-cp39-abi3-win32.whl", hash = "sha256:9b336599e2cb77b1008cb2ac264b290803ec5e8e89d618a5e978ff5eb6f715d9"},
+    {file = "cryptography-44.0.1-cp39-abi3-win_amd64.whl", hash = "sha256:e403f7f766ded778ecdb790da786b418a9f2394f36e8cc8b796cc056ab05f44f"},
+    {file = "cryptography-44.0.1-pp310-pypy310_pp73-macosx_10_9_x86_64.whl", hash = "sha256:1f9a92144fa0c877117e9748c74501bea842f93d21ee00b0cf922846d9d0b183"},
+    {file = "cryptography-44.0.1-pp310-pypy310_pp73-manylinux_2_28_aarch64.whl", hash = "sha256:610a83540765a8d8ce0f351ce42e26e53e1f774a6efb71eb1b41eb01d01c3d12"},
+    {file = "cryptography-44.0.1-pp310-pypy310_pp73-manylinux_2_28_x86_64.whl", hash = "sha256:5fed5cd6102bb4eb843e3315d2bf25fede494509bddadb81e03a859c1bc17b83"},
+    {file = "cryptography-44.0.1-pp310-pypy310_pp73-manylinux_2_34_aarch64.whl", hash = "sha256:f4daefc971c2d1f82f03097dc6f216744a6cd2ac0f04c68fb935ea2ba2a0d420"},
+    {file = "cryptography-44.0.1-pp310-pypy310_pp73-manylinux_2_34_x86_64.whl", hash = "sha256:94f99f2b943b354a5b6307d7e8d19f5c423a794462bde2bf310c770ba052b1c4"},
+    {file = "cryptography-44.0.1-pp310-pypy310_pp73-win_amd64.whl", hash = "sha256:d9c5b9f698a83c8bd71e0f4d3f9f839ef244798e5ffe96febfa9714717db7af7"},
+    {file = "cryptography-44.0.1.tar.gz", hash = "sha256:f51f5705ab27898afda1aaa430f34ad90dc117421057782022edf0600bec5f14"},
 ]
 
 [package.dependencies]
-cffi = ">=1.12"
+cffi = {version = ">=1.12", markers = "platform_python_implementation != \"PyPy\""}
 
 [package.extras]
-docs = ["sphinx (>=5.3.0)", "sphinx-rtd-theme (>=1.1.1)"]
-docstest = ["pyenchant (>=1.6.11)", "sphinxcontrib-spelling (>=4.0.1)", "twine (>=1.12.0)"]
-nox = ["nox"]
-pep8test = ["black", "check-sdist", "mypy", "ruff"]
-sdist = ["build"]
+docs = ["sphinx (>=5.3.0)", "sphinx-rtd-theme (>=3.0.0)"]
+docstest = ["pyenchant (>=3)", "readme-renderer (>=30.0)", "sphinxcontrib-spelling (>=7.3.1)"]
+nox = ["nox (>=2024.4.15)", "nox[uv] (>=2024.3.2)"]
+pep8test = ["check-sdist", "click (>=8.0.1)", "mypy (>=1.4)", "ruff (>=0.3.6)"]
+sdist = ["build (>=1.0.0)"]
 ssh = ["bcrypt (>=3.1.5)"]
-test = ["pretend", "pytest (>=6.2.0)", "pytest-benchmark", "pytest-cov", "pytest-xdist"]
+test = ["certifi (>=2024)", "cryptography-vectors (==44.0.1)", "pretend (>=0.7)", "pytest (>=7.4.0)", "pytest-benchmark (>=4.0)", "pytest-cov (>=2.10.1)", "pytest-xdist (>=3.5.0)"]
 test-randomorder = ["pytest-randomly"]
 
 [[package]]
@@ -406,13 +414,13 @@ files = [
 
 [[package]]
 name = "paramiko"
-version = "3.2.0"
+version = "3.4.0"
 description = "SSH2 protocol library"
 optional = false
 python-versions = ">=3.6"
 files = [
-    {file = "paramiko-3.2.0-py3-none-any.whl", hash = "sha256:df0f9dd8903bc50f2e10580af687f3015bf592a377cd438d2ec9546467a14eb8"},
-    {file = "paramiko-3.2.0.tar.gz", hash = "sha256:93cdce625a8a1dc12204439d45033f3261bdb2c201648cfcdc06f9fd0f94ec29"},
+    {file = "paramiko-3.4.0-py3-none-any.whl", hash = "sha256:43f0b51115a896f9c00f59618023484cb3a14b98bbceab43394a39c6739b7ee7"},
+    {file = "paramiko-3.4.0.tar.gz", hash = "sha256:aac08f26a31dc4dffd92821527d1682d99d52f9ef6851968114a8728f3c274d3"},
 ]
 
 [package.dependencies]
@@ -580,6 +588,7 @@ files = [
     {file = "PyYAML-6.0.1-cp310-cp310-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:69b023b2b4daa7548bcfbd4aa3da05b3a74b772db9e23b982788168117739938"},
     {file = "PyYAML-6.0.1-cp310-cp310-manylinux_2_17_s390x.manylinux2014_s390x.whl", hash = "sha256:81e0b275a9ecc9c0c0c07b4b90ba548307583c125f54d5b6946cfee6360c733d"},
     {file = "PyYAML-6.0.1-cp310-cp310-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:ba336e390cd8e4d1739f42dfe9bb83a3cc2e80f567d8805e11b46f4a943f5515"},
+    {file = "PyYAML-6.0.1-cp310-cp310-musllinux_1_1_x86_64.whl", hash = "sha256:326c013efe8048858a6d312ddd31d56e468118ad4cdeda36c719bf5bb6192290"},
     {file = "PyYAML-6.0.1-cp310-cp310-win32.whl", hash = "sha256:bd4af7373a854424dabd882decdc5579653d7868b8fb26dc7d0e99f823aa5924"},
     {file = "PyYAML-6.0.1-cp310-cp310-win_amd64.whl", hash = "sha256:fd1592b3fdf65fff2ad0004b5e363300ef59ced41c2e6b3a99d4089fa8c5435d"},
     {file = "PyYAML-6.0.1-cp311-cp311-macosx_10_9_x86_64.whl", hash = "sha256:6965a7bc3cf88e5a1c3bd2e0b5c22f8d677dc88a455344035f03399034eb3007"},
@@ -587,8 +596,16 @@ files = [
     {file = "PyYAML-6.0.1-cp311-cp311-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:42f8152b8dbc4fe7d96729ec2b99c7097d656dc1213a3229ca5383f973a5ed6d"},
     {file = "PyYAML-6.0.1-cp311-cp311-manylinux_2_17_s390x.manylinux2014_s390x.whl", hash = "sha256:062582fca9fabdd2c8b54a3ef1c978d786e0f6b3a1510e0ac93ef59e0ddae2bc"},
     {file = "PyYAML-6.0.1-cp311-cp311-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:d2b04aac4d386b172d5b9692e2d2da8de7bfb6c387fa4f801fbf6fb2e6ba4673"},
+    {file = "PyYAML-6.0.1-cp311-cp311-musllinux_1_1_x86_64.whl", hash = "sha256:e7d73685e87afe9f3b36c799222440d6cf362062f78be1013661b00c5c6f678b"},
     {file = "PyYAML-6.0.1-cp311-cp311-win32.whl", hash = "sha256:1635fd110e8d85d55237ab316b5b011de701ea0f29d07611174a1b42f1444741"},
     {file = "PyYAML-6.0.1-cp311-cp311-win_amd64.whl", hash = "sha256:bf07ee2fef7014951eeb99f56f39c9bb4af143d8aa3c21b1677805985307da34"},
+    {file = "PyYAML-6.0.1-cp312-cp312-macosx_10_9_x86_64.whl", hash = "sha256:855fb52b0dc35af121542a76b9a84f8d1cd886ea97c84703eaa6d88e37a2ad28"},
+    {file = "PyYAML-6.0.1-cp312-cp312-macosx_11_0_arm64.whl", hash = "sha256:40df9b996c2b73138957fe23a16a4f0ba614f4c0efce1e9406a184b6d07fa3a9"},
+    {file = "PyYAML-6.0.1-cp312-cp312-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:a08c6f0fe150303c1c6b71ebcd7213c2858041a7e01975da3a99aed1e7a378ef"},
+    {file = "PyYAML-6.0.1-cp312-cp312-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:6c22bec3fbe2524cde73d7ada88f6566758a8f7227bfbf93a408a9d86bcc12a0"},
+    {file = "PyYAML-6.0.1-cp312-cp312-musllinux_1_1_x86_64.whl", hash = "sha256:8d4e9c88387b0f5c7d5f281e55304de64cf7f9c0021a3525bd3b1c542da3b0e4"},
+    {file = "PyYAML-6.0.1-cp312-cp312-win32.whl", hash = "sha256:d483d2cdf104e7c9fa60c544d92981f12ad66a457afae824d146093b8c294c54"},
+    {file = "PyYAML-6.0.1-cp312-cp312-win_amd64.whl", hash = "sha256:0d3304d8c0adc42be59c5f8a4d9e3d7379e6955ad754aa9d6ab7a398b59dd1df"},
     {file = "PyYAML-6.0.1-cp36-cp36m-macosx_10_9_x86_64.whl", hash = "sha256:50550eb667afee136e9a77d6dc71ae76a44df8b3e51e41b77f6de2932bfe0f47"},
     {file = "PyYAML-6.0.1-cp36-cp36m-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:1fe35611261b29bd1de0070f0b2f47cb6ff71fa6595c077e42bd0c419fa27b98"},
     {file = "PyYAML-6.0.1-cp36-cp36m-manylinux_2_17_s390x.manylinux2014_s390x.whl", hash = "sha256:704219a11b772aea0d8ecd7058d0082713c3562b4e271b849ad7dc4a5c90c13c"},
@@ -605,6 +622,7 @@ files = [
     {file = "PyYAML-6.0.1-cp38-cp38-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:a0cd17c15d3bb3fa06978b4e8958dcdc6e0174ccea823003a106c7d4d7899ac5"},
     {file = "PyYAML-6.0.1-cp38-cp38-manylinux_2_17_s390x.manylinux2014_s390x.whl", hash = "sha256:28c119d996beec18c05208a8bd78cbe4007878c6dd15091efb73a30e90539696"},
     {file = "PyYAML-6.0.1-cp38-cp38-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:7e07cbde391ba96ab58e532ff4803f79c4129397514e1413a7dc761ccd755735"},
+    {file = "PyYAML-6.0.1-cp38-cp38-musllinux_1_1_x86_64.whl", hash = "sha256:49a183be227561de579b4a36efbb21b3eab9651dd81b1858589f796549873dd6"},
     {file = "PyYAML-6.0.1-cp38-cp38-win32.whl", hash = "sha256:184c5108a2aca3c5b3d3bf9395d50893a7ab82a38004c8f61c258d4428e80206"},
     {file = "PyYAML-6.0.1-cp38-cp38-win_amd64.whl", hash = "sha256:1e2722cc9fbb45d9b87631ac70924c11d3a401b2d7f410cc0e3bbf249f2dca62"},
     {file = "PyYAML-6.0.1-cp39-cp39-macosx_10_9_x86_64.whl", hash = "sha256:9eb6caa9a297fc2c2fb8862bc5370d0303ddba53ba97e71f08023b6cd73d16a8"},
@@ -612,6 +630,7 @@ files = [
     {file = "PyYAML-6.0.1-cp39-cp39-manylinux_2_17_aarch64.manylinux2014_aarch64.whl", hash = "sha256:5773183b6446b2c99bb77e77595dd486303b4faab2b086e7b17bc6bef28865f6"},
     {file = "PyYAML-6.0.1-cp39-cp39-manylinux_2_17_s390x.manylinux2014_s390x.whl", hash = "sha256:b786eecbdf8499b9ca1d697215862083bd6d2a99965554781d0d8d1ad31e13a0"},
     {file = "PyYAML-6.0.1-cp39-cp39-manylinux_2_17_x86_64.manylinux2014_x86_64.whl", hash = "sha256:bc1bf2925a1ecd43da378f4db9e4f799775d6367bdb94671027b73b393a7c42c"},
+    {file = "PyYAML-6.0.1-cp39-cp39-musllinux_1_1_x86_64.whl", hash = "sha256:04ac92ad1925b2cff1db0cfebffb6ffc43457495c9b3c39d3fcae417d7125dc5"},
     {file = "PyYAML-6.0.1-cp39-cp39-win32.whl", hash = "sha256:faca3bdcf85b2fc05d06ff3fbc1f83e1391b3e724afa3feba7d13eeab355484c"},
     {file = "PyYAML-6.0.1-cp39-cp39-win_amd64.whl", hash = "sha256:510c9deebc5c0225e8c96813043e62b680ba2f9c50a08d3724c7f28a747d1486"},
     {file = "PyYAML-6.0.1.tar.gz", hash = "sha256:bfdf460b1736c775f2ba9f6a92bca30bc2095067b8a9d77876d1fad6cc3b4a43"},

diff --git a/dpdk/kernel/linux/igb_uio/Kbuild b/dpdk/kernel/linux/igb_uio/Kbuild
new file mode 100644 (file)
index 0000000..3ab85c4
--- /dev/null
+++ b/dpdk/kernel/linux/igb_uio/Kbuild
@@ -0,0 +1,2 @@
+ccflags-y := $(MODULE_CFLAGS)
+obj-m := igb_uio.o

diff --git a/dpdk/kernel/linux/igb_uio/Makefile b/dpdk/kernel/linux/igb_uio/Makefile
new file mode 100644 (file)
index 0000000..bd2e356
--- /dev/null
+++ b/dpdk/kernel/linux/igb_uio/Makefile
@@ -0,0 +1,7 @@
+KSRC ?= /lib/modules/$(shell uname -r)/build
+
+all:
+       make -C $(KSRC)/ M=$(CURDIR)
+
+%:
+       make -C $(KSRC)/ M=$(CURDIR) $@

diff --git a/dpdk/kernel/linux/igb_uio/compat.h b/dpdk/kernel/linux/igb_uio/compat.h
new file mode 100644 (file)
index 0000000..71172f4
--- /dev/null
+++ b/dpdk/kernel/linux/igb_uio/compat.h
@@ -0,0 +1,168 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Minimal wrappers to allow compiling igb_uio on older kernels.
+ */
+
+#ifndef RHEL_RELEASE_VERSION
+#define RHEL_RELEASE_VERSION(a, b) (((a) << 8) + (b))
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
+#define pci_cfg_access_lock   pci_block_user_cfg_access
+#define pci_cfg_access_unlock pci_unblock_user_cfg_access
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)
+#define HAVE_PTE_MASK_PAGE_IOMAP
+#endif
+
+#ifndef PCI_MSIX_ENTRY_SIZE
+#define PCI_MSIX_ENTRY_SIZE            16
+#define PCI_MSIX_ENTRY_VECTOR_CTRL     12
+#define PCI_MSIX_ENTRY_CTRL_MASKBIT    1
+#endif
+
+/*
+ * for kernels < 2.6.38 and backported patch that moves MSI-X entry definition
+ * to pci_regs.h Those kernels has PCI_MSIX_ENTRY_SIZE defined but not
+ * PCI_MSIX_ENTRY_CTRL_MASKBIT
+ */
+#ifndef PCI_MSIX_ENTRY_CTRL_MASKBIT
+#define PCI_MSIX_ENTRY_CTRL_MASKBIT    1
+#endif
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 34) && \
+       (!(defined(RHEL_RELEASE_CODE) && \
+        RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(5, 9)))
+
+static int pci_num_vf(struct pci_dev *dev)
+{
+       struct iov {
+               int pos;
+               int nres;
+               u32 cap;
+               u16 ctrl;
+               u16 total;
+               u16 initial;
+               u16 nr_virtfn;
+       } *iov = (struct iov *)dev->sriov;
+
+       if (!dev->is_physfn)
+               return 0;
+
+       return iov->nr_virtfn;
+}
+
+#endif /* < 2.6.34 */
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39) && \
+       (!(defined(RHEL_RELEASE_CODE) && \
+          RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 4)))
+
+#define kstrtoul strict_strtoul
+
+#endif /* < 2.6.39 */
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0) && \
+       (!(defined(RHEL_RELEASE_CODE) && \
+          RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(6, 3)))
+
+/* Check if INTX works to control irq's.
+ * Set's INTX_DISABLE flag and reads it back
+ */
+static bool pci_intx_mask_supported(struct pci_dev *pdev)
+{
+       bool mask_supported = false;
+       uint16_t orig, new;
+
+       pci_block_user_cfg_access(pdev);
+       pci_read_config_word(pdev, PCI_COMMAND, &orig);
+       pci_write_config_word(pdev, PCI_COMMAND,
+                             orig ^ PCI_COMMAND_INTX_DISABLE);
+       pci_read_config_word(pdev, PCI_COMMAND, &new);
+
+       if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
+               dev_err(&pdev->dev, "Command register changed from "
+                       "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
+       } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
+               mask_supported = true;
+               pci_write_config_word(pdev, PCI_COMMAND, orig);
+       }
+       pci_unblock_user_cfg_access(pdev);
+
+       return mask_supported;
+}
+
+static bool pci_check_and_mask_intx(struct pci_dev *pdev)
+{
+       bool pending;
+       uint32_t status;
+
+       pci_block_user_cfg_access(pdev);
+       pci_read_config_dword(pdev, PCI_COMMAND, &status);
+
+       /* interrupt is not ours, goes to out */
+       pending = (((status >> 16) & PCI_STATUS_INTERRUPT) != 0);
+       if (pending) {
+               uint16_t old, new;
+
+               old = status;
+               if (status != 0)
+                       new = old & (~PCI_COMMAND_INTX_DISABLE);
+               else
+                       new = old | PCI_COMMAND_INTX_DISABLE;
+
+               if (old != new)
+                       pci_write_config_word(pdev, PCI_COMMAND, new);
+       }
+       pci_unblock_user_cfg_access(pdev);
+
+       return pending;
+}
+
+#endif /* < 3.3.0 */
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)
+#define HAVE_PCI_IS_BRIDGE_API 1
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0)
+#define HAVE_MSI_LIST_IN_GENERIC_DEVICE 1
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 5, 0)
+#define HAVE_PCI_MSI_MASK_IRQ 1
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0)
+#define HAVE_ALLOC_IRQ_VECTORS 1
+#endif
+
+static inline bool igbuio_kernel_is_locked_down(void)
+{
+#ifdef CONFIG_LOCK_DOWN_KERNEL
+#ifdef CONFIG_LOCK_DOWN_IN_EFI_SECURE_BOOT
+       return kernel_is_locked_down(NULL);
+#elif defined(CONFIG_EFI_SECURE_BOOT_LOCK_DOWN)
+       return kernel_is_locked_down();
+#else
+       return false;
+#endif
+#else
+       return false;
+#endif
+}
+
+#ifndef fallthrough
+
+#ifndef __has_attribute
+#define __has_attribute(x) 0
+#endif
+
+#if __has_attribute(__fallthrough__)
+#define fallthrough    __attribute__((__fallthrough__))
+#else
+#define fallthrough    do {} while (0)  /* fallthrough */
+#endif
+
+#endif

diff --git a/dpdk/kernel/linux/igb_uio/igb_uio.c b/dpdk/kernel/linux/igb_uio/igb_uio.c
new file mode 100644 (file)
index 0000000..aea67da
--- /dev/null
+++ b/dpdk/kernel/linux/igb_uio/igb_uio.c
@@ -0,0 +1,668 @@
+// SPDX-License-Identifier: GPL-2.0
+/*-
+ * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/uio_driver.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/msi.h>
+#include <linux/version.h>
+#include <linux/slab.h>
+
+/**
+ * These enum and macro definitions are copied from the
+ * file rte_pci_dev_features.h
+ */
+enum rte_intr_mode {
+       RTE_INTR_MODE_NONE = 0,
+       RTE_INTR_MODE_LEGACY,
+       RTE_INTR_MODE_MSI,
+       RTE_INTR_MODE_MSIX
+};
+#define RTE_INTR_MODE_NONE_NAME "none"
+#define RTE_INTR_MODE_LEGACY_NAME "legacy"
+#define RTE_INTR_MODE_MSI_NAME "msi"
+#define RTE_INTR_MODE_MSIX_NAME "msix"
+
+
+#include "compat.h"
+
+/**
+ * A structure describing the private information for a uio device.
+ */
+struct rte_uio_pci_dev {
+       struct uio_info info;
+       struct pci_dev *pdev;
+       enum rte_intr_mode mode;
+       atomic_t refcnt;
+};
+
+static int wc_activate;
+static char *intr_mode;
+static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
+/* sriov sysfs */
+static ssize_t
+show_max_vfs(struct device *dev, struct device_attribute *attr,
+            char *buf)
+{
+       return snprintf(buf, 10, "%u\n", dev_num_vf(dev));
+}
+
+static ssize_t
+store_max_vfs(struct device *dev, struct device_attribute *attr,
+             const char *buf, size_t count)
+{
+       int err = 0;
+       unsigned long max_vfs;
+       struct pci_dev *pdev = to_pci_dev(dev);
+
+       if (0 != kstrtoul(buf, 0, &max_vfs))
+               return -EINVAL;
+
+       if (0 == max_vfs)
+               pci_disable_sriov(pdev);
+       else if (0 == pci_num_vf(pdev))
+               err = pci_enable_sriov(pdev, max_vfs);
+       else /* do nothing if change max_vfs number */
+               err = -EINVAL;
+
+       return err ? err : count;
+}
+
+static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
+
+static struct attribute *dev_attrs[] = {
+       &dev_attr_max_vfs.attr,
+       NULL,
+};
+
+static const struct attribute_group dev_attr_grp = {
+       .attrs = dev_attrs,
+};
+
+#ifndef HAVE_PCI_MSI_MASK_IRQ
+/*
+ * It masks the msix on/off of generating MSI-X messages.
+ */
+static void
+igbuio_msix_mask_irq(struct msi_desc *desc, s32 state)
+{
+       u32 mask_bits = desc->masked;
+       unsigned int offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
+                                               PCI_MSIX_ENTRY_VECTOR_CTRL;
+
+       if (state != 0)
+               mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
+       else
+               mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
+
+       if (mask_bits != desc->masked) {
+               writel(mask_bits, desc->mask_base + offset);
+               readl(desc->mask_base);
+               desc->masked = mask_bits;
+       }
+}
+
+/*
+ * It masks the msi on/off of generating MSI messages.
+ */
+static void
+igbuio_msi_mask_irq(struct pci_dev *pdev, struct msi_desc *desc, int32_t state)
+{
+       u32 mask_bits = desc->masked;
+       u32 offset = desc->irq - pdev->irq;
+       u32 mask = 1 << offset;
+
+       if (!desc->msi_attrib.maskbit)
+               return;
+
+       if (state != 0)
+               mask_bits &= ~mask;
+       else
+               mask_bits |= mask;
+
+       if (mask_bits != desc->masked) {
+               pci_write_config_dword(pdev, desc->mask_pos, mask_bits);
+               desc->masked = mask_bits;
+       }
+}
+
+static void
+igbuio_mask_irq(struct pci_dev *pdev, enum rte_intr_mode mode, s32 irq_state)
+{
+       struct msi_desc *desc;
+       struct list_head *msi_list;
+
+#ifdef HAVE_MSI_LIST_IN_GENERIC_DEVICE
+       msi_list = &pdev->dev.msi_list;
+#else
+       msi_list = &pdev->msi_list;
+#endif
+
+       if (mode == RTE_INTR_MODE_MSIX) {
+               list_for_each_entry(desc, msi_list, list)
+                       igbuio_msix_mask_irq(desc, irq_state);
+       } else if (mode == RTE_INTR_MODE_MSI) {
+               list_for_each_entry(desc, msi_list, list)
+                       igbuio_msi_mask_irq(pdev, desc, irq_state);
+       }
+}
+#endif
+
+/**
+ * This is the irqcontrol callback to be registered to uio_info.
+ * It can be used to disable/enable interrupt from user space processes.
+ *
+ * @param info
+ *  pointer to uio_info.
+ * @param irq_state
+ *  state value. 1 to enable interrupt, 0 to disable interrupt.
+ *
+ * @return
+ *  - On success, 0.
+ *  - On failure, a negative value.
+ */
+static int
+igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
+{
+       struct rte_uio_pci_dev *udev = info->priv;
+       struct pci_dev *pdev = udev->pdev;
+
+#ifdef HAVE_PCI_MSI_MASK_IRQ
+       struct irq_data *irq = irq_get_irq_data(udev->info.irq);
+#endif
+
+       pci_cfg_access_lock(pdev);
+
+       if (udev->mode == RTE_INTR_MODE_MSIX || udev->mode == RTE_INTR_MODE_MSI) {
+#ifdef HAVE_PCI_MSI_MASK_IRQ
+               if (irq_state == 1)
+                       pci_msi_unmask_irq(irq);
+               else
+                       pci_msi_mask_irq(irq);
+#else
+               igbuio_mask_irq(pdev, udev->mode, irq_state);
+#endif
+       }
+
+       if (udev->mode == RTE_INTR_MODE_LEGACY)
+               pci_intx(pdev, !!irq_state);
+
+       pci_cfg_access_unlock(pdev);
+
+       return 0;
+}
+
+/**
+ * This is interrupt handler which will check if the interrupt is for the right device.
+ * If yes, disable it here and will be enable later.
+ */
+static irqreturn_t
+igbuio_pci_irqhandler(int irq, void *dev_id)
+{
+       struct rte_uio_pci_dev *udev = (struct rte_uio_pci_dev *)dev_id;
+       struct uio_info *info = &udev->info;
+
+       /* Legacy mode need to mask in hardware */
+       if (udev->mode == RTE_INTR_MODE_LEGACY &&
+           !pci_check_and_mask_intx(udev->pdev))
+               return IRQ_NONE;
+
+       uio_event_notify(info);
+
+       /* Message signal mode, no share IRQ and automasked */
+       return IRQ_HANDLED;
+}
+
+static int
+igbuio_pci_enable_interrupts(struct rte_uio_pci_dev *udev)
+{
+       int err = 0;
+#ifndef HAVE_ALLOC_IRQ_VECTORS
+       struct msix_entry msix_entry;
+#endif
+
+       switch (igbuio_intr_mode_preferred) {
+       case RTE_INTR_MODE_MSIX:
+               /* Only 1 msi-x vector needed */
+#ifndef HAVE_ALLOC_IRQ_VECTORS
+               msix_entry.entry = 0;
+               if (pci_enable_msix(udev->pdev, &msix_entry, 1) == 0) {
+                       dev_dbg(&udev->pdev->dev, "using MSI-X");
+                       udev->info.irq_flags = IRQF_NO_THREAD;
+                       udev->info.irq = msix_entry.vector;
+                       udev->mode = RTE_INTR_MODE_MSIX;
+                       break;
+               }
+#else
+               if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSIX) == 1) {
+                       dev_dbg(&udev->pdev->dev, "using MSI-X");
+                       udev->info.irq_flags = IRQF_NO_THREAD;
+                       udev->info.irq = pci_irq_vector(udev->pdev, 0);
+                       udev->mode = RTE_INTR_MODE_MSIX;
+                       break;
+               }
+#endif
+
+       fallthrough;
+       case RTE_INTR_MODE_MSI:
+#ifndef HAVE_ALLOC_IRQ_VECTORS
+               if (pci_enable_msi(udev->pdev) == 0) {
+                       dev_dbg(&udev->pdev->dev, "using MSI");
+                       udev->info.irq_flags = IRQF_NO_THREAD;
+                       udev->info.irq = udev->pdev->irq;
+                       udev->mode = RTE_INTR_MODE_MSI;
+                       break;
+               }
+#else
+               if (pci_alloc_irq_vectors(udev->pdev, 1, 1, PCI_IRQ_MSI) == 1) {
+                       dev_dbg(&udev->pdev->dev, "using MSI");
+                       udev->info.irq_flags = IRQF_NO_THREAD;
+                       udev->info.irq = pci_irq_vector(udev->pdev, 0);
+                       udev->mode = RTE_INTR_MODE_MSI;
+                       break;
+               }
+#endif
+       fallthrough;
+       case RTE_INTR_MODE_LEGACY:
+               if (pci_intx_mask_supported(udev->pdev)) {
+                       dev_dbg(&udev->pdev->dev, "using INTX");
+                       udev->info.irq_flags = IRQF_SHARED | IRQF_NO_THREAD;
+                       udev->info.irq = udev->pdev->irq;
+                       udev->mode = RTE_INTR_MODE_LEGACY;
+                       break;
+               }
+               dev_notice(&udev->pdev->dev, "PCI INTX mask not supported\n");
+       fallthrough;
+       case RTE_INTR_MODE_NONE:
+               udev->mode = RTE_INTR_MODE_NONE;
+               udev->info.irq = UIO_IRQ_NONE;
+               break;
+
+       default:
+               dev_err(&udev->pdev->dev, "invalid IRQ mode %u",
+                       igbuio_intr_mode_preferred);
+               udev->info.irq = UIO_IRQ_NONE;
+               err = -EINVAL;
+       }
+
+       if (udev->info.irq != UIO_IRQ_NONE)
+               err = request_irq(udev->info.irq, igbuio_pci_irqhandler,
+                                 udev->info.irq_flags, udev->info.name,
+                                 udev);
+       dev_info(&udev->pdev->dev, "uio device registered with irq %ld\n",
+                udev->info.irq);
+
+       return err;
+}
+
+static void
+igbuio_pci_disable_interrupts(struct rte_uio_pci_dev *udev)
+{
+       if (udev->info.irq) {
+               free_irq(udev->info.irq, udev);
+               udev->info.irq = 0;
+       }
+
+#ifndef HAVE_ALLOC_IRQ_VECTORS
+       if (udev->mode == RTE_INTR_MODE_MSIX)
+               pci_disable_msix(udev->pdev);
+       if (udev->mode == RTE_INTR_MODE_MSI)
+               pci_disable_msi(udev->pdev);
+#else
+       if (udev->mode == RTE_INTR_MODE_MSIX ||
+           udev->mode == RTE_INTR_MODE_MSI)
+               pci_free_irq_vectors(udev->pdev);
+#endif
+}
+
+
+/**
+ * This gets called while opening uio device file.
+ */
+static int
+igbuio_pci_open(struct uio_info *info, struct inode *inode)
+{
+       struct rte_uio_pci_dev *udev = info->priv;
+       struct pci_dev *dev = udev->pdev;
+       int err;
+
+       if (atomic_inc_return(&udev->refcnt) != 1)
+               return 0;
+
+       /* set bus master, which was cleared by the reset function */
+       pci_set_master(dev);
+
+       /* enable interrupts */
+       err = igbuio_pci_enable_interrupts(udev);
+       if (err) {
+               atomic_dec(&udev->refcnt);
+               dev_err(&dev->dev, "Enable interrupt fails\n");
+       }
+       return err;
+}
+
+static int
+igbuio_pci_release(struct uio_info *info, struct inode *inode)
+{
+       struct rte_uio_pci_dev *udev = info->priv;
+       struct pci_dev *dev = udev->pdev;
+
+       if (atomic_dec_and_test(&udev->refcnt)) {
+               /* disable interrupts */
+               igbuio_pci_disable_interrupts(udev);
+
+               /* stop the device from further DMA */
+               pci_clear_master(dev);
+       }
+
+       return 0;
+}
+
+/* Remap pci resources described by bar #pci_bar in uio resource n. */
+static int
+igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
+                      int n, int pci_bar, const char *name)
+{
+       unsigned long addr, len;
+       void *internal_addr;
+
+       if (n >= ARRAY_SIZE(info->mem))
+               return -EINVAL;
+
+       addr = pci_resource_start(dev, pci_bar);
+       len = pci_resource_len(dev, pci_bar);
+       if (addr == 0 || len == 0)
+               return -1;
+       if (wc_activate == 0) {
+               internal_addr = ioremap(addr, len);
+               if (internal_addr == NULL)
+                       return -1;
+       } else {
+               internal_addr = NULL;
+       }
+       info->mem[n].name = name;
+       info->mem[n].addr = addr;
+       info->mem[n].internal_addr = internal_addr;
+       info->mem[n].size = len;
+       info->mem[n].memtype = UIO_MEM_PHYS;
+       return 0;
+}
+
+/* Get pci port io resources described by bar #pci_bar in uio resource n. */
+static int
+igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
+               int n, int pci_bar, const char *name)
+{
+       unsigned long addr, len;
+
+       if (n >= ARRAY_SIZE(info->port))
+               return -EINVAL;
+
+       addr = pci_resource_start(dev, pci_bar);
+       len = pci_resource_len(dev, pci_bar);
+       if (addr == 0 || len == 0)
+               return -EINVAL;
+
+       info->port[n].name = name;
+       info->port[n].start = addr;
+       info->port[n].size = len;
+       info->port[n].porttype = UIO_PORT_X86;
+
+       return 0;
+}
+
+/* Unmap previously ioremap'd resources */
+static void
+igbuio_pci_release_iomem(struct uio_info *info)
+{
+       int i;
+
+       for (i = 0; i < MAX_UIO_MAPS; i++) {
+               if (info->mem[i].internal_addr)
+                       iounmap(info->mem[i].internal_addr);
+       }
+}
+
+static int
+igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
+{
+       int i, iom, iop, ret;
+       unsigned long flags;
+       static const char *bar_names[PCI_STD_RESOURCE_END + 1]  = {
+               "BAR0",
+               "BAR1",
+               "BAR2",
+               "BAR3",
+               "BAR4",
+               "BAR5",
+       };
+
+       iom = 0;
+       iop = 0;
+
+       for (i = 0; i < ARRAY_SIZE(bar_names); i++) {
+               if (pci_resource_len(dev, i) != 0 &&
+                               pci_resource_start(dev, i) != 0) {
+                       flags = pci_resource_flags(dev, i);
+                       if (flags & IORESOURCE_MEM) {
+                               ret = igbuio_pci_setup_iomem(dev, info, iom,
+                                                            i, bar_names[i]);
+                               if (ret != 0)
+                                       return ret;
+                               iom++;
+                       } else if (flags & IORESOURCE_IO) {
+                               ret = igbuio_pci_setup_ioport(dev, info, iop,
+                                                             i, bar_names[i]);
+                               if (ret != 0)
+                                       return ret;
+                               iop++;
+                       }
+               }
+       }
+
+       return (iom != 0 || iop != 0) ? ret : -ENOENT;
+}
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
+static int __devinit
+#else
+static int
+#endif
+igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+       struct rte_uio_pci_dev *udev;
+       dma_addr_t map_dma_addr;
+       void *map_addr;
+       int err;
+
+#ifdef HAVE_PCI_IS_BRIDGE_API
+       if (pci_is_bridge(dev)) {
+               dev_warn(&dev->dev, "Ignoring PCI bridge device\n");
+               return -ENODEV;
+       }
+#endif
+
+       udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
+       if (!udev)
+               return -ENOMEM;
+
+       /*
+        * enable device: ask low-level code to enable I/O and
+        * memory
+        */
+       err = pci_enable_device(dev);
+       if (err != 0) {
+               dev_err(&dev->dev, "Cannot enable PCI device\n");
+               goto fail_free;
+       }
+
+       /* enable bus mastering on the device */
+       pci_set_master(dev);
+
+       /* remap IO memory */
+       err = igbuio_setup_bars(dev, &udev->info);
+       if (err != 0)
+               goto fail_release_iomem;
+
+       /* set 64-bit DMA mask */
+       err = dma_set_mask_and_coherent(&dev->dev,  DMA_BIT_MASK(64));
+       if (err != 0) {
+               dev_err(&dev->dev, "Cannot set DMA mask\n");
+               goto fail_release_iomem;
+       }
+
+       /* fill uio infos */
+       udev->info.name = "igb_uio";
+       udev->info.version = "0.1";
+       udev->info.irqcontrol = igbuio_pci_irqcontrol;
+       udev->info.open = igbuio_pci_open;
+       udev->info.release = igbuio_pci_release;
+       udev->info.priv = udev;
+       udev->pdev = dev;
+       atomic_set(&udev->refcnt, 0);
+
+       err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
+       if (err != 0)
+               goto fail_release_iomem;
+
+       /* register uio driver */
+       err = uio_register_device(&dev->dev, &udev->info);
+       if (err != 0)
+               goto fail_remove_group;
+
+       pci_set_drvdata(dev, udev);
+
+       /*
+        * Doing a harmless dma mapping for attaching the device to
+        * the iommu identity mapping if kernel boots with iommu=pt.
+        * Note this is not a problem if no IOMMU at all.
+        */
+       map_addr = dma_alloc_coherent(&dev->dev, 1024, &map_dma_addr,
+                       GFP_KERNEL);
+       if (map_addr)
+               memset(map_addr, 0, 1024);
+
+       if (!map_addr)
+               dev_info(&dev->dev, "dma mapping failed\n");
+       else {
+               dev_info(&dev->dev, "mapping 1K dma=%#llx host=%p\n",
+                        (unsigned long long)map_dma_addr, map_addr);
+
+               dma_free_coherent(&dev->dev, 1024, map_addr, map_dma_addr);
+               dev_info(&dev->dev, "unmapping 1K dma=%#llx host=%p\n",
+                        (unsigned long long)map_dma_addr, map_addr);
+       }
+
+       return 0;
+
+fail_remove_group:
+       sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
+fail_release_iomem:
+       igbuio_pci_release_iomem(&udev->info);
+       pci_disable_device(dev);
+fail_free:
+       kfree(udev);
+
+       return err;
+}
+
+static void
+igbuio_pci_remove(struct pci_dev *dev)
+{
+       struct rte_uio_pci_dev *udev = pci_get_drvdata(dev);
+
+       igbuio_pci_release(&udev->info, NULL);
+
+       sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
+       uio_unregister_device(&udev->info);
+       igbuio_pci_release_iomem(&udev->info);
+       pci_disable_device(dev);
+       pci_set_drvdata(dev, NULL);
+       kfree(udev);
+}
+
+static int
+igbuio_config_intr_mode(char *intr_str)
+{
+       if (!intr_str) {
+               pr_info("Use MSIX interrupt by default\n");
+               return 0;
+       }
+
+       if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
+               igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
+               pr_info("Use MSIX interrupt\n");
+       } else if (!strcmp(intr_str, RTE_INTR_MODE_MSI_NAME)) {
+               igbuio_intr_mode_preferred = RTE_INTR_MODE_MSI;
+               pr_info("Use MSI interrupt\n");
+       } else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
+               igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
+               pr_info("Use legacy interrupt\n");
+       } else {
+               pr_info("Error: bad parameter - %s\n", intr_str);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static struct pci_driver igbuio_pci_driver = {
+       .name = "igb_uio",
+       .id_table = NULL,
+       .probe = igbuio_pci_probe,
+       .remove = igbuio_pci_remove,
+};
+
+static int __init
+igbuio_pci_init_module(void)
+{
+       int ret;
+
+       if (igbuio_kernel_is_locked_down()) {
+               pr_err("Not able to use module, kernel lock down is enabled\n");
+               return -EINVAL;
+       }
+
+       if (wc_activate != 0)
+               pr_info("wc_activate is set\n");
+
+       ret = igbuio_config_intr_mode(intr_mode);
+       if (ret < 0)
+               return ret;
+
+       return pci_register_driver(&igbuio_pci_driver);
+}
+
+static void __exit
+igbuio_pci_exit_module(void)
+{
+       pci_unregister_driver(&igbuio_pci_driver);
+}
+
+module_init(igbuio_pci_init_module);
+module_exit(igbuio_pci_exit_module);
+
+module_param(intr_mode, charp, S_IRUGO);
+MODULE_PARM_DESC(intr_mode,
+"igb_uio interrupt mode (default=msix):\n"
+"    " RTE_INTR_MODE_MSIX_NAME "       Use MSIX interrupt\n"
+"    " RTE_INTR_MODE_MSI_NAME "        Use MSI interrupt\n"
+"    " RTE_INTR_MODE_LEGACY_NAME "     Use Legacy interrupt\n"
+"\n");
+
+module_param(wc_activate, int, 0);
+MODULE_PARM_DESC(wc_activate,
+"Activate support for write combining (WC) (default=0)\n"
+"    0 - disable\n"
+"    other - enable\n");
+
+MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Intel Corporation");

diff --git a/dpdk/kernel/linux/igb_uio/meson.build b/dpdk/kernel/linux/igb_uio/meson.build
new file mode 100644 (file)
index 0000000..b52a5ae
--- /dev/null
+++ b/dpdk/kernel/linux/igb_uio/meson.build
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017 Intel Corporation
+
+# Copy source files to build directory
+src_files = ['igb_uio.c', 'Kbuild', 'compat.h']
+foreach src : src_files
+    configure_file(
+        input: src,
+        output: src,
+        copy: true,
+    )
+endforeach
+
+mkfile = custom_target('igb_uio_makefile',
+        output: 'Makefile',
+        command: ['touch', '@OUTPUT@'])
+
+custom_target('igb_uio',
+        input: src_files,  # Now using the copied files in build dir
+        output: 'igb_uio.ko',
+        command: ['make', '-C', kernel_build_dir,
+                'M=' + meson.current_build_dir(),
+                'src=' + meson.current_source_dir(),
+                'EXTRA_CFLAGS=-I' + meson.current_source_dir() +
+                        '/../../../lib/librte_eal/include',
+                'modules'],
+        depends: mkfile,
+        install: true,
+        install_dir: kernel_build_dir + '/extra/dpdk',
+        build_by_default: get_option('enable_kmods'))

diff --git a/dpdk/kernel/linux/meson.build b/dpdk/kernel/linux/meson.build
new file mode 100644 (file)
index 0000000..7558fb9
--- /dev/null
+++ b/dpdk/kernel/linux/meson.build
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2018 Intel Corporation
+
+subdirs = ['igb_uio']
+
+kernel_build_dir = get_option('kernel_dir')
+kernel_source_dir = get_option('kernel_dir')
+kernel_install_dir = ''
+install = not meson.is_cross_build()
+cross_args = []
+
+if not meson.is_cross_build()
+    # native build
+    kernel_version = run_command('uname', '-r', check: true).stdout().strip()
+    if kernel_source_dir != ''
+        # Try kernel release from sources first
+        r = run_command('make', '-s', '-C', kernel_source_dir, 'kernelrelease', check: false)
+        if r.returncode() == 0
+            kernel_version = r.stdout().strip()
+        endif
+    else
+        # use default path for native builds
+        kernel_source_dir = '/lib/modules/' + kernel_version + '/source'
+    endif
+    kernel_install_dir = '/lib/modules/' + kernel_version + '/extra/dpdk'
+    if kernel_build_dir == ''
+        # use default path for native builds
+        kernel_build_dir = '/lib/modules/' + kernel_version + '/build'
+    endif
+
+    # test running make in kernel directory, using "make kernelversion"
+    make_returncode = run_command('make', '-sC', kernel_build_dir,
+            'kernelversion', check: true).returncode()
+    if make_returncode != 0
+        # backward compatibility:
+        # the headers could still be in the 'build' subdir
+        if not kernel_build_dir.endswith('build') and not kernel_build_dir.endswith('build/')
+            kernel_build_dir = join_paths(kernel_build_dir, 'build')
+            make_returncode = run_command('make', '-sC', kernel_build_dir,
+                    'kernelversion', check: true).returncode()
+        endif
+    endif
+
+    if make_returncode != 0
+        error('Cannot compile kernel modules as requested - are kernel headers installed?')
+    endif
+
+    # DO ACTUAL MODULE BUILDING
+    foreach d:subdirs
+        subdir(d)
+    endforeach
+
+    subdir_done()
+endif
+
+# cross build
+# if we are cross-compiling we need kernel_build_dir specified
+if kernel_build_dir == ''
+    error('Need "kernel_dir" option for kmod compilation when cross-compiling')
+endif
+cross_compiler = find_program('c').path()
+if cross_compiler.endswith('gcc')
+    cross_prefix = run_command([py3, '-c', 'print("' + cross_compiler + '"[:-3])'],
+            check: true).stdout().strip()
+elif cross_compiler.endswith('clang')
+    cross_prefix = ''
+    found_target = false
+    # search for '-target' and use the arg that follows
+    # (i.e. the value of '-target') as cross_prefix
+    foreach cross_c_arg : meson.get_cross_property('c_args')
+        if found_target and cross_prefix == ''
+            cross_prefix = cross_c_arg
+        endif
+        if cross_c_arg == '-target'
+            found_target = true
+        endif
+    endforeach
+    if cross_prefix == ''
+        error('Did not find -target and its value in c_args in input cross-file.')
+    endif
+    linker = 'lld'
+    foreach cross_c_link_arg : meson.get_cross_property('c_link_args')
+        if cross_c_link_arg.startswith('-fuse-ld')
+            linker = cross_c_link_arg.split('=')[1]
+        endif
+    endforeach
+    cross_args += ['CC=@0@'.format(cross_compiler), 'LD=ld.@0@'.format(linker)]
+else
+    error('Unsupported cross compiler: @0@'.format(cross_compiler))
+endif
+
+cross_arch = host_machine.cpu_family()
+if host_machine.cpu_family() == 'aarch64'
+    cross_arch = 'arm64'
+endif
+
+cross_args += ['ARCH=@0@'.format(cross_arch),
+        'CROSS_COMPILE=@0@'.format(cross_prefix)]
+
+# DO ACTUAL MODULE BUILDING
+foreach d:subdirs
+    subdir(d)
+endforeach

diff --git a/dpdk/kernel/meson.build b/dpdk/kernel/meson.build
index 417735b010a7fe27d1cefd97abc42189cecf37d6..282842bcbaf577ee6695c6f3b9f89595478a361e 100644 (file)
--- a/dpdk/kernel/meson.build
+++ b/dpdk/kernel/meson.build
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2017 Intel Corporation
 
-if is_freebsd
+#if is_freebsd
     subdir(exec_env)
-endif
+#endif

diff --git a/dpdk/lib/eal/freebsd/include/rte_os.h b/dpdk/lib/eal/freebsd/include/rte_os.h
index 003468caff9c7cdacf121968aa4896546a3b01d1..576b786cabd720d8d78189ea4bf1c44a64263af2 100644 (file)
--- a/dpdk/lib/eal/freebsd/include/rte_os.h
+++ b/dpdk/lib/eal/freebsd/include/rte_os.h
@@ -30,6 +30,22 @@ typedef cpuset_t rte_cpuset_t;
 #define RTE_HAS_CPUSET
 
 #ifdef RTE_EAL_FREEBSD_CPUSET_LEGACY
+#if __FreeBSD_version >= 1301000
+#define RTE_CPU_AND(dst, src1, src2) do \
+{ \
+       cpuset_t tmp; \
+       CPU_COPY(src1, &tmp); \
+       CPU_AND(&tmp, &tmp, src2); \
+       CPU_COPY(&tmp, dst); \
+} while (0)
+#define RTE_CPU_OR(dst, src1, src2) do \
+{ \
+       cpuset_t tmp; \
+       CPU_COPY(src1, &tmp); \
+       CPU_OR(&tmp, &tmp, src2); \
+       CPU_COPY(&tmp, dst); \
+} while (0)
+#else
 #define RTE_CPU_AND(dst, src1, src2) do \
 { \
        cpuset_t tmp; \
@@ -44,6 +60,7 @@ typedef cpuset_t rte_cpuset_t;
        CPU_OR(&tmp, src2); \
        CPU_COPY(&tmp, dst); \
 } while (0)
+#endif
 #define RTE_CPU_FILL(set) CPU_FILL(set)
 
 /* In FreeBSD 13 CPU_NAND macro is CPU_ANDNOT */
@@ -56,6 +73,15 @@ typedef cpuset_t rte_cpuset_t;
        CPU_COPY(&tmp, dst); \
 } while (0)
 #else
+if __FreeBSD_version >= 1301000
+#define RTE_CPU_NOT(dst, src) do \
+{ \
+       cpuset_t tmp; \
+       CPU_FILL(&tmp); \
+       CPU_ANDNOT(&tmp, &tmp, src); \
+       CPU_COPY(&tmp, dst); \
+} while (0)
+#else
 #define RTE_CPU_NOT(dst, src) do \
 { \
        cpuset_t tmp; \
@@ -63,6 +89,7 @@ typedef cpuset_t rte_cpuset_t;
        CPU_ANDNOT(&tmp, src); \
        CPU_COPY(&tmp, dst); \
 } while (0)
+#endif
 #endif /* CPU_NAND */
 
 #else /* RTE_EAL_FREEBSD_CPUSET_LEGACY */