]> git.feebdaed.xyz Git - 0xmirror/dpdk.git/commitdiff
net/mlx5/windows: fix match criteria in flow creation
authorItai Sharoni <isharoni@nvidia.com>
Mon, 17 Nov 2025 08:45:00 +0000 (10:45 +0200)
committerRaslan Darawsheh <rasland@nvidia.com>
Tue, 18 Nov 2025 13:20:19 +0000 (14:20 +0100)
Currently the Windows implementation hardcodes match criteria to
MLX5_MATCH_OUTER_HEADERS when creating flow rules, which prevents
matching on inner headers and other criteria types like NVGRE.

The fix uses the matcher's match_criteria_enable attribute instead
of hardcoding OUTER_HEADERS, and moves the assignment outside the
action switch block to apply to all cases.

NVGRE item type is also added to the supported items list.

Fixes: 1d194496b9d1 ("net/mlx5: create flow rule on Windows")
Cc: stable@dpdk.org
Signed-off-by: Itai Sharoni <isharoni@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
.mailmap
doc/guides/nics/mlx5.rst
drivers/net/mlx5/windows/mlx5_flow_os.c
drivers/net/mlx5/windows/mlx5_flow_os.h

index efc66fd48c1bfaa2aaedf5342ba914fa79ff563a..2f089326ff1e3098432b7398f85fb92fe516a053 100644 (file)
--- a/.mailmap
+++ b/.mailmap
@@ -639,6 +639,7 @@ Ilyes Ben Hamouda <ilyes.ben_hamouda@6wind.com>
 Intiyaz Basha <intiyaz.basha@caviumnetworks.com>
 Ioana Ciornei <ioana.ciornei@nxp.com>
 Isaac Boukris <iboukris@gmail.com>
+Itai Sharoni <isharoni@nvidia.com>
 Itamar Gozlan <igozlan@nvidia.com>
 Itsuro Oda <oda@valinux.co.jp>
 Ivan Boule <ivan.boule@6wind.com>
index 2cf95578deb041079b80027b1523a9cb5ce36c56..51d7637fba22a54802a7ec0e9b01e3b4b1bad55c 100644 (file)
@@ -1231,6 +1231,10 @@ On Windows, the features are limited:
   - IPv4/TCP with CVLAN filtering
   - L4 steering rules for port RSS of IP, UDP, TCP
 
+- Tunnel protocol support:
+
+  - NVGRE (requires DevX dynamic insertion mode)
+
 
 .. _mlx5_multiproc:
 
index 7a625fb880ac0fdbf405b60660613dde43350cc7..15c6fc56133bf7f255856619f2c631a0539dfcbf 100644 (file)
@@ -219,9 +219,9 @@ mlx5_flow_os_create_flow(void *matcher, void *match_value,
                default:
                        break;
                }
-               MLX5_SET(devx_fs_rule_add_in, in, match_criteria_enable,
-                        MLX5_MATCH_OUTER_HEADERS);
        }
+       MLX5_SET(devx_fs_rule_add_in, in, match_criteria_enable,
+               mlx5_matcher->attr.match_criteria_enable);
        *flow = mlx5_glue->devx_fs_rule_add(mlx5_matcher->ctx, in, sizeof(in));
        return (*flow) ? 0 : -1;
 }
index 2cd4e9532565ef78e5c031860e8cd1f11b7c4043..c087bca4bef269aac85991d8b9c1e22e7b894db9 100644 (file)
@@ -47,6 +47,7 @@ mlx5_flow_os_item_supported(int item)
        case RTE_FLOW_ITEM_TYPE_IPV6:
        case RTE_FLOW_ITEM_TYPE_VLAN:
        case RTE_FLOW_ITEM_TYPE_ESP:
+       case RTE_FLOW_ITEM_TYPE_NVGRE:
                return true;
        default:
                return false;